74act11867 synchronous 8-bit up/down binary counter with asynchronous clear scas178a ? december 1991 ? revised february 1998 1 post office box 655303 ? dallas, texas 75265 inputs are ttl-voltage compatible asynchronous clear fully independent clock circuit simplifies use flow-through architecture optimizes pcb layout center-pin v cc and gnd configurations minimize high-speed switching noise epic ? (enhanced-performance implanted cmos) 1- m process 500-ma typical latch-up immunity at 125 c description the 74act11867 is a synchronous presettable binary counter featuring an internal carry look-ahead for cascading in high-speed counting applications. synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. this mode of operation helps eliminate the output counting spikes that are normally associated with asynchronous (ripple-clock) counters. a buffered clock (clk) input triggers the eight flip-flops on the rising (positive-going) edge of the clock waveform. the counters are fully programmable; that is, the outputs can each be preset to either logic level. the load-mode circuitry allows parallel loading of the cascaded counters. as loading is synchronous, selecting the load mode disables the counter and causes the outputs to agree with the data inputs after the next clock rising edge. the carry look-ahead circuitry is provided for cascading counters for n-bit synchronous applications without additional gating. this is done with two count-enable inputs and a carry output. both count-enable (enp and ent ) inputs must be low to count. the direction of the count is determined by the levels of the select (s0 and s1) inputs (see the function table). input ent is fed forward to enable the ripple-carry (rco ) output. rco then produces a low-level pulse while the count is zero (all outputs low) when counting down or 255 during counting up (all outputs high). this low-level overflow carry pulse can be used to enable successive cascaded stages. transitions at enp and ent are allowed regardless of the level of the clock input. these c ounters feature a fully independent clock circuit. whenever enp and/or ent is taken high, rco either goes high or remains high. the function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times. the 74act11867 is characterized for operation from ?40 c to 85 c. copyright ? 1998, texas instruments incorporated production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. epic is a trademark of texas instruments incorporated. please be aware that an important notice concerning avail ability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. q a q b q c q d q e gnd gnd gnd gnd q f q g q h rco clk dw package (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a b c d e f v cc v cc g h enp ent s0 s1
74act11867 synchronous 8-bit up/down binary counter with asynchronous clear scas178a ? december 1991 ? revised february 1998 2 post office box 655303 ? dallas, texas 75265 mode function table s1 s0 function l l clear l h count down h l load h h count up logic symbol ? 2,6d 28 a 27 b 26 c 25 d 1 2 3 4 ent ctrdiv256 0 16 s0 g4 17 c6/1,4,5?/3,4,5+ 13 1,4,5ct = 0 3,4,5ct = 255 24 e 23 f 20 g 19 h 5 10 11 12 1 15 s1 g5 18 14 clk enp rco 0 3 m 0r 0 q a q b q c q d q e q f q g q h ? this symbol is in accordance with ansi/ieee std 91-1984 and iec publication 617-12.
74act11867 synchronous 8-bit up/down binary counter with asynchronous clear scas178a ? december 1991 ? revised february 1998 3 post office box 655303 ? dallas, texas 75265 logic diagram (positive logic) rco ent enp 1d c1 r clk s0 s1 a b c d e f g h 17 19 20 23 24 25 26 27 28 18 15 16 14 1 2 3 4 5 10 11 12 13 q q q q q q q q h g f e d c b a 1d c1 r 1d c1 r 1d c1 r 1d c1 r 1d c1 r 1d c1 r 1d c1 r
74act11867 synchronous 8-bit up/down binary counter with asynchronous clear scas178a ? december 1991 ? revised february 1998 4 post office box 655303 ? dallas, texas 75265 output sequence count up c async clear inhibit ? 012 d e f clk enp ent q a q b q c q d rco data inputs outputs q e q f q g q h count down 1 0 255 254 253 252 255 254 253 g h b a s1 s0 preset outputs to 252 ? ent and enp must both be low for counting to occur.
74act11867 synchronous 8-bit up/down binary counter with asynchronous clear scas178a ? december 1991 ? revised february 1998 5 post office box 655303 ? dallas, texas 75265 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) ? supply voltage range, v cc ?0.5 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, v i (see note 1) ?0.5 v to v cc + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range, v o (see note 1) ?0.5 v to v cc + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input clamp current, i ik (v i < 0 or v i > v cc ) 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output clamp current, i ok (v o < 0 or v o > v cc ) 50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous output current, i o (v o = 0 to v cc ) 50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous current through v cc or gnd 225 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . package thermal impedance, ja (see note 2): dw package 78 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg ?65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, a nd functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating conditi ons? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. notes: 1. the input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. the package thermal impedance is calculated in accordance with jesd 51. recommended operating conditions (see note 3) min nom max unit v cc supply voltage 4.5 5 5.5 v v ih high-level input voltage 2 v v il low-level input voltage 0.8 v v i input voltage 0 v cc v v o output voltage 0 v cc v i oh high-level output current ?24 ma i ol low-level output current 24 ma t/ v input transition rise or fall rate 0 10 ns/v t a operating free-air temperature ?40 85 c note 3: all unused inputs of the device must be held at v cc or gnd to ensure proper device operation. refer to the ti application report, implications of slow or floating cmos inputs , literature number scba004.
74act11867 synchronous 8-bit up/down binary counter with asynchronous clear scas178a ? december 1991 ? revised february 1998 6 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions v t a = 25 c min max unit parameter test conditions v cc min typ max min max unit i 50 a 4.5 v 4.4 4.4 i oh = ?50 a 5.5 v 5.4 5.4 v oh i oh = ?24 ma 4.5 v 3.94 3.8 v v oh i oh = ? 24 ma 5.5 v 4.94 4.8 v i oh = ?75 ma ? 5.5 v 3.85 i 50 a 4.5 v 0.1 0.1 i ol = 50 a 5.5 v 0.1 0.1 v ol i 24 ma 4.5 v 0.36 0.44 v v ol i ol = 24 ma 5.5 v 0.36 0.44 v i ol = 75 ma ? 5.5 v 1.65 i i v i = v cc or gnd 5.5 v 0.1 1 a i cc v i = v cc or gnd, i o = 0 5.5 v 8 80 a i cc ? one input at 3.4 v, other inputs at v cc or gnd 5.5 v 0.9 1 ma c i v i = v cc or gnd 5 v 4.5 pf ? not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. ? this is the increase in supply current for each input that is at one of the specified ttl voltage levels rather than 0 v or v cc . timing requirements over recommended operating free-air temperature range, v cc = 5 v 0.5 v (unless otherwise noted) (see figure 1) t a = 25 c min max unit min max min max unit f clock clock frequency 0 70 0 70 mhz t pulse duration s0 and s1 low 12 12 ns t w pulse duration clk 6.5 6.5 ns data 8 8 enp , ent 4 4 t su setup time before clk s0, s1 (load) 11 11 ns t su setup time before clk data 1 1 ns t skew skew time between s0 and s1 to avoid inadvertent clear ? s0 and s1 low 0 0 ns this setup time is required to ensure stable data. ? this is the maximum time for which s0 and s1 can be low simultaneously when the device transitions between the load (s1 = h, s0 = l) and count-down (s1 = l, s0 = h) modes.
74act11867 synchronous 8-bit up/down binary counter with asynchronous clear scas178a ? december 1991 ? revised february 1998 7 post office box 655303 ? dallas, texas 75265 switching characteristics over recommended operating free-air temperature range, v cc = 5 v 0.5 v (unless otherwise noted) (see figure 1) parameter from to t a = 25 c min max unit parameter from (input) to (output) min typ max min max unit f max 70 70 mhz t plh clk rco 6 9.9 12.7 6 14.6 ns t phl clk rco 6.4 10.9 14.2 6.4 16.3 ns t plh clk q 5 8.9 11.9 5 13.6 ns t phl clk q 4.9 9 12.2 4.9 14 ns t plh ent rco 3.9 6.8 9.1 3.9 10.5 ns t phl ent rco 3.1 7 10.2 3.1 11.5 ns t phl clear (s0, s1 low) q 6.3 11.9 16.6 6.3 19.1 ns t s0, s1 rco 55 10 4 15 6 55 17 8 ns t plh s0 , s1 (count up/down) rco 5.5 10.4 15.6 5.5 17.8 ns t s0, s1 rco 56 10 1 14 8 56 17 2 ns t phl s0 , s1 (count up/down) rco 5.6 10.1 14.8 5.6 17.2 ns t phl clear (s0, s1 low) rco 6.2 11.3 15.6 6.2 17.8 ns operating characteristics, v cc = 5 v, t a = 25 c parameter test conditions typ unit c pd power dissipation capacitance c l = 50 pf, f = 1 mhz 62 pf
74act11867 synchronous 8-bit up/down binary counter with asynchronous clear scas178a ? december 1991 ? revised february 1998 8 post office box 655303 ? dallas, texas 75265 parameter measurement information 50% v cc 1.5 v 1.5 v 1.5 v 3 v 3 v 0 v 0 v t h t su voltage waveforms data input t plh t phl t phl t plh v oh v ol v ol 1.5 v 1.5 v 3 v 0 v 50% v cc 50% v cc input (see note b) out-of-phase output in-phase output timing input (see note b) voltage waveforms 3 v 0 v 1.5 v 1.5 v t w voltage waveforms input load circuit from output under test c l = 50 pf (see note a) 500 notes: a. c l includes probe and jig capacitance. b. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 , t r = 3 ns, t f = 3 ns. c. the outputs are measured one at a time with one input transition per measurement. 50% v cc v oh figure 1. load circuit and voltage waveforms
package option addendum www.ti.com 11-apr-2013 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) op temp (c) top-side markings (4) samples 74ACT11867DW obsolete soic dw 28 tbd call ti call ti -40 to 85 74ACT11867DWr obsolete soic dw 28 tbd call ti call ti -40 to 85 74act11867nt obsolete pdip nt 28 tbd call ti call ti -40 to 85 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) multiple top-side markings will be inside parentheses. only one top-side marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire top-side marking for that device. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
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